Field
This disclosure relates generally to semiconductor device packaging, and more specifically, to packages with multiple semiconductor die.
Related Art
Package substrates for semiconductor devices such as leadframes and ceramic or laminate substrates provide a central supporting structure of molded IC packages to which all other elements of the molded IC package are attached. Package substrates are etched, stamped or formed with a thin sheet of material with a pattern of terminals around a central die attach platform upon which a die is mounted using, for example, an epoxy resin. The die includes bonding pads which are electrically connected to the surrounding lead terminals of the frame by conductive wires using well-established wirebond techniques. The assembly including the package substrate, die, and wires are covered with encapsulant material to complete the molded IC package.
The demand for smaller devices with higher throughput and capability is ever increasing. Thus, there is a continuing need to find ways to fit more semiconductor processing, memory, and/or sensor devices in the smallest space possible including stacking an IC package on top of another IC package, which is referred to as package on package (PoP) technology. The typical PoP arrangement is the memory package mounted on top of processor. The connections between two packages with various PoP technologies all rely on solder balls, e.g. flip chip PoP, ball grid array (BGA) PoP and through mold via (TMV) PoP. With the growth of complexity of processors and density of memory, a fine pitch connection between two packages is required, however the stand-off or distance between packages required for the top package may prevent smaller solder ball size to achieve finer pitch, e.g. 0.25 mm solder ball for 0.4 mm pitch. At same time, the solder ball size constrains thickness of the bottom package which limits the size of the processor and increases the packaging cost.